Kev Ua Tau Zoo:
ARM + FPGA dual-chip architecture, 3kHz ceev voj bandwidth, 250µs synchronous voj voog, ntau-axis sib koom tes teb sai thiab meej, xyuas kom meej tias kev ua haujlwm du yam tsis muaj lag.
Kev Sib Tw Muaj Zog:
Sib xws nrog cov chaw tsim khoom PLC loj 'Ethernet-based fieldbus systems, ua kom muaj kev sib koom ua ke nrog cov khoom siv tshiab thiab cov khoom siv uas twb muaj lawm.
Cov neeg siv-kho tau I/O Interfaces:
9 DI inputs (suav nrog 2 lub zog ceev probe) thiab 6 DO outputs, txhawb nqa ob qho tib si qhib-collector thiab sib txawv zaus faib cov zis interfaces.
Nruab nrog built-in regenerative resistor.
Hom Kev Tswj:
Txoj hauj lwm, qhov ceev, torque, thiab kev tswj hwm lub voj voog sib xyaw.
Cov yam ntxwv ntawm Servo muaj xws li:
Kev txo kev co, kev txheeb xyuas inertia, thiab kev kho servo yooj yim (lub rooj rigidity txheem).
Tau tshaj nrog cov motors ntsuas los ntawm 50W txog 3000W.
Cov cav uas muaj 23-bit magnetic/optical encoders.
Xaiv tau nres nres
Muaj STO (Safe Torque Off) function
Tus Rtelligent R6Cov koob sawv cev rau qhov siab tshaj plaws ntawm kev siv tshuab servo, kev sib txuas cov algorithms R-AI tshiab nrog kev tsim kho vajtse tshiab. Zoo tagnrho rau cov khoom siv automation siab kawg uas kev ua tau zoo, kev ua haujlwm raug, thiab kev hloov pauv tseem ceeb tshaj plaws.
Cov koob Rtelligent R6 muaj qhov kev daws teeb meem siab dua 64 × piv rau cov encoders 17-ntsis (131,072), ua tiav qhov tseeb ntawm qhov chaw tsis muaj qhov sib piv. Nws xa cov lus txib kom taug qab sai dua thiab txo lub sijhawm teeb tsa, ua rau cov tshuab ua haujlwm sai dua thiab txhawb kev tsim khoom Muaj lub ARM + FPGA dual-chip architecture ua haujlwm siab nrog 250 μs synchronization cycle, cov kev daws teeb meem no muab kev ua tau zoo dua rau cov ntawv thov interpolation-demanding. Nrog kev txhawb nqa rau txhua lub tsheb npav hauv kev lag luam, STO kev nyab xeeb tau lees paub, thiab kev kho tsis siv neeg, nws yog qhov kev hloov kho servo kawg rau kev lag luam uas muaj kev ua haujlwm siab.






